The contract manufacturer is in no hurry to offer GAAFET, which seems like a good strategy at the moment.
A TSMC He even outlined the manufacturing techniques he came up with in the summer, but at that time the 3 and 2 nm nodes did not receive as much attention, although they were included in the plans at the male level. Now the contractor was talking about these actions, so it turned out roughly what to expect in the future.
At 3nm bandwidth, the company is still sticking to its FinFET transistor architecture, so it can offer trial production for its first 3nm node labeled N3 relatively soon, which will happen this year, while mass production will begin in the second half of next year, mostly towards the end of general. This process will provide 1.7 times better transistor density compared to the 5nm node, with up to 30% better data consumption and 15% better power consumption. There will also be a second generation of 3nm node with N3E signals, which will follow the first year from now and can be considered a kind of improvement.
The 2nm bandwidth already makes a big difference, as TSMC will also move to the newer GAAFET transistor architecture, which will provide significant benefits. The company has set 2025 as the target date here, which likely means mass production will begin, but there is no data for what period of the year in question to indicate.